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Low Skew,1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL Fanout Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG20
Lead Count (#):20
Pkg. Dimensions (mm):6.5 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)20
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)74
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Country of AssemblyTAIWAN
Country of Wafer FabricationSINGAPORE
Additive Phase Jitter Typ RMS (fs)90
Additive Phase Jitter Typ RMS (ps)0.09
Core Voltage (V)3.3
FunctionBuffer, Multiplexer
Input Freq (MHz)266
Input TypeLVCMOS
Inputs (#)2
Length (mm)6.5
MOQ148
Output Banks (#)1
Output Freq Range (MHz)266
Output Skew (ps)30
Output TypeLVPECL
Output Voltage (V)3.3
Outputs (#)4
Package Area (mm²)28.6
Pitch (mm)0.65
Pkg. Dimensions (mm)6.5 x 4.4 x 1.0
Pkg. TypeTSSOP
Price (USD)$3.25313
Product CategoryClock Buffers & Drivers, Clock Multiplexers
PublishedNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

Description

The 8535I-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The 8535I-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8535I-01 ideal for those applications demanding well defined performance and repeatability.