Package Information
| Lead Count (#) | 68 |
| Pkg. Type | VFQFPN |
| Pkg. Code | NLG68 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 0.85 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
| Moisture Sensitivity Level (MSL) | 3 |
Product Attributes
| Pkg. Type | VFQFPN |
| Lead Count (#) | 68 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| Advanced Features | Programmable Clock |
| App Jitter Compliance | GR-253-CORE (OC-12), ITU-T G.813 (STM-16/Option 1) |
| Core Voltage (V) | 3.3 |
| Input Freq (MHz) | 0.002 - 155.52 |
| Input Type | LVCMOS |
| Inputs (#) | 4 |
| Length (mm) | 10 |
| MOQ | 42 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 0.000001 - 155.52 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 100.0 |
| Pb Free Category | e3 Sn |
| Phase Jitter Typ RMS (ps) | 100.000 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 10.0 x 10.0 x 0.85 |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Qty. per Carrier (#) | 168 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range | 0 to 70°C |
| Thickness (mm) | 0.85 |
| Width (mm) | 10 |
Description
The 82V32021 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. An input clock is automatically or manually selected for DPLL locking. The DPLL supports three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0 APLL, the outputs of the device will be in a better jitter/wander performance. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed only through an I2C programming interface.