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3.3V CMOS 12-Bit to 24-Bit Multiplexed D-Type Latch with 3-State Outputs, Bus-Hold

Package Information

Lead Count (#) 56
Pkg. Type TSSOP
Pkg. Code PAG56
Pitch (mm) 0.5
Pkg. Dimensions (mm) 14.0 x 6.1 x 1.0

Environmental & Export Classifications

Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390000
Moisture Sensitivity Level (MSL) 1

Product Attributes

Pkg. Type TSSOP
Lead Count (#) 56
Pb (Lead) Free Yes
Carrier Type Reel
Bus Width (bits) 24
Core Voltage (V) 3.3
Function Latch
Length (mm) 14.0
MOQ 2000
Moisture Sensitivity Level (MSL) 1
Output Type 3-state
Package Area (mm²) 85.4
Pb Free Category e3 Sn
Pitch (mm) 0.5
Pkg. Dimensions (mm) 14.0 x 6.1 x 1.0
Qty. per Carrier (#) 0
Qty. per Reel (#) 2000
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Speed Grade Standard
Tape & Reel Yes
Temp. Range -40 to 85°C
Thickness (mm) 1.0
Width (mm) 6.1

Description

The 74ALVCH16260 12-bit to 24-bit multiplexed D-type latch is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. The 74ALVCH16260 has "bus-hold" which prevents floating inputs and eliminates the need for pull-up/down resistors. The 74ALVCH16260 operates at -40C to +85C