Overview
Description
The 72V205 is a 256 x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock (WCLK) for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.
Features
- 10ns read/write cycle time
- 5V input tolerant
- Renesas Standard or First Word Fall Through timing
- Single or double register-buffered Empty and Full flags
- Easily expandable in depth and width
- Asynchronous or coincident Read and Write clocks
- Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings
- Half-Full flag capability
- Output enable puts the output data bus in a high-impedance state
- Available in 64-pin TQFP and STQFP packages
- Industrial temperature range (–40 °C to +85 °C) is available
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Support
Support Communities
Get quick technical support online from Renesas Engineering Community technical staff.
