Features
- High system speed 200MHz (3.1ns clock access time)
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
- 3.3V core power supply
- Power down controlled by ZZ input
- 2.5V I/O
- Optional - Boundary Scan JTAG interface (IEEE 1149.1 compliant)
- Available in 100-pin TQFP and 119-pin BGA packages
Description
The 71V25761 3.3V CMOS synchronous SRAM is organized as 128K x 36 and contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.
Parameters
| Attributes | Value |
|---|---|
| Density (Kb) | 4608 |
| Bus Width (bits) | 36 |
| Core Voltage (V) | 3.3 |
| Pkg. Code | PKG100 |
| Organization | 128K x 36 |
| I/O Voltage (V) | 2.5 - 2.5 |
| I/O Frequency (MHz) | 183 - 183 |
| Temp. Range (°C) | -40 to 85°C |
| Architecture | Synch Burst |
| Output Type | Pipelined |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 20.0 x 14.0 x 1.4 | 100 | 0.65 |