Features
- High-speed address/chip select time – Military: 25/35/45/55/70/85/100ns (max.)
- Commercial/Industrial: 20/25/35ns (max.) low power only
- Low-power operation
- Battery Backup operation – 2V data retention
- Input and output directly TTL-compatible
- Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (300 mil) SOJ
- Military product compliant to MIL-STD-883, Class B
Description
The 71256 5V CMOS SRAM is organized as 32K x 8. The circuit also offers a reduced power standby mode for significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Military grade product is available.
Support Communities
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WHITE_LIST in DSPS_HOST project
Hi Dialog Q1: Is there any doc related how to use the WHITE_LIST for multible slve to one central connection ?? Q2 : As per my understanding in order to use WHITE_LIST => STEP 1 :In DSPS_HOST project i have to configure all my slaves(7 as per DSPS_HOST ...
Sep 26, 2016 -
Could not find 'vendor.renesas.graphics.composer
... query. [ 6.700639] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 6.709191] rcar-du feb00000.display: DU0 use CMM(Double buffer) [ 6.712568] ehci-platform: EHCI generic platform driver [ 6.716279] rcar-du feb00000.display: DU1 use CMM(Double buffer) [ 6.731309] rcar-du feb00000.display: DU2 ...
Dec 3, 2024 -
IDT71256L25DB STAM related
... last power off condition even after a power recycling. We have come across literature describing the data remanence property and would like to understand it better. We are also curious if the phenomenon is tested by manufacturer. Could you please provide information on data remanence, especially on SRAM like 71256L25DB.
Jun 27, 2025
Support Communities
