Features
- Commercial (0C to +70C), Industrial (–40C to +85C)
- Equal access and cycle times — Commercial and Industrial: 12/15/20ns
- Two Chip Selects plus one Output Enable pin
- Bidirectional inputs and outputs directly TTL-compatible
- Low power consumption via chip deselect
- Available in 300 and 400 mil Plastic SOJ packages
71024 - Block Diagram
Description
The 71024 5V CMOS SRAM is organized as 128K x 8. All bidirectional inputs and outputs of the 71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
Parameters
| Attributes | Value |
|---|---|
| Density (Kb) | 1024 |
| Bus Width (bits) | 8 |
| Core Voltage (V) | 5 |
| Organization | 128K x 8 |
| I/O Voltage (V) | 5 - 5 |
| Access Time (ns) | 15, 20 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Asynchronous |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| SOJ | 21.95 x 7.6 x 2.67 | 32 | 1.27 |
Support Communities
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Booting from SPI Master
Hi, I'm little confused with AN-B-001 - "DA1458x Booting from serial interfaces". In Table 2: SPI Master boot protocol, when ACK/NACK will be received? - when sending the zero byte or - when sending the LS byte of the length? Also, according the last row of the table ...
Sep 1, 2016
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