Overview
Description
The 71024 5V CMOS SRAM is organized as 128K x 8. All bidirectional inputs and outputs of the 71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
Features
- Commercial (0C to +70C), Industrial (–40C to +85C)
- Equal access and cycle times — Commercial and Industrial: 12/15/20ns
- Two Chip Selects plus one Output Enable pin
- Bidirectional inputs and outputs directly TTL-compatible
- Low power consumption via chip deselect
- Available in 300 and 400 mil Plastic SOJ packages
Comparison
Applications
Documentation
Featured Documentation
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| Datasheet | PDF 204 KB | |
| Guide | PDF 207 KB 日本語 | |
| Guide | PDF 1.27 MB 日本語 | |
| End Of Life Notice | PDF 938 KB | |
| End Of Life Notice | PDF 909 KB | |
| Product Change Notice | PDF 748 KB | |
| Product Change Notice | PDF 108 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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Booting from SPI Master
Hi, I'm little confused with AN-B-001 - "DA1458x Booting from serial interfaces". In Table 2: SPI Master boot protocol, when ACK/NACK will be received? - when sending the zero byte or - when sending the LS byte of the length? Also, according the last row of the table ...
Sep 1, 2016