Features
- True Dual-Ported memory cells which allow simultaneous access of the same memory location
- Dual chip enables allow for depth expansion without external logic
- 70V28 easily expands data bus width to 32 bits or more
- Busy and Interrupt Flags
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility
- LVTTL-compatible, single 3.3V (±0.3V) power supply
- Available in a 100-pin TQFP package
- Industrial temperature range (–40C to +85C) is available
70V28 - Block Diagram
Description
The 70V28 is a high-speed 64K x 16 Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or wider memory system applications resulting in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.
Parameters
| Attributes | Value |
|---|---|
| Core Voltage (V) | 3.3 |
| Bus Width (bits) | 16 |
| Density (Kb) | 1024 |
| Pkg. Code | PNG100 |
| Interface | Async |
| I/O Type | 3.3 V LVTTL |
| Access Time (ns) | 15, 20 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 64K x 16 |
| Function | Busy, Interrupt, Master, Semaphore, Slave |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TQFP | 14.0 x 14.0 x 1.4 | 100 | 0.5 |
Support Communities
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Requesting sample code to test the 70V28L dual port sram
Hello team,we have connected dpram to the verdin base board through the gpio pins which are free to use. we have connected D0 to D7 data pins and A0 A15 pins. we want to perform write and read operations. Can you please provide me the any sample code (like ...
Jan 23, 2025
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