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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.

Serially Programmable Clock Source for Freescale Systems

Package Information

CAD Model:View CAD Model
Pkg. Type:SOIC
Pkg. Code:DCG16
Lead Count (#):16
Pkg. Dimensions (mm):9.9 x 3.9 x 1.5
Pitch (mm):1.27

Environmental & Export Classifications

Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
Moisture Sensitivity Level (MSL)3

Product Attributes

Pkg. TypeSOIC
Lead Count (#)16
Pb (Lead) FreeYes
Carrier TypeTube
Core Voltage (V)3.3V, 5V
Input Freq (KHz)5 - 27
Input Freq (MHz)25 - 25
Inputs (#)1
Length (mm)9.9
MOQ144
Moisture Sensitivity Level (MSL)3
Output Freq Range (MHz)6 - 200
Output SignalingLVTTL
Output Voltage (V)5V, 3.3V
Outputs (#)2
Package Area (mm²)38.6
Pb Free Categorye3 Sn
Phase Jitter Typ RMS (ps)0.34
Pitch (mm)1.27
Pkg. Dimensions (mm)9.9 x 3.9 x 1.5
Qty. per Carrier (#)48
Qty. per Reel (#)0
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Temp. Range (°C)-40 to 85°C
Thickness (mm)1.5
Width (mm)3.9
Xtal Freq (KHz)5 - 27
Xtal Inputs (#)1

Description

The 6V40277 is a small, versatile serially programmable clock source for Freescale systems. It can generate any frequency from 6MHz to 200MHz and has a second configurable output. The outputs can be reprogrammed on the fly and will lock to a new frequency in 10ms or less. Smooth transitions (in which the clock duty cycle remains near 50%) are guaranteed if the output divider is not changed. The device includes a PDTS pin which tri-states the output clocks and powers down the entire chip. The 6V40277 features a default clock output at start-up. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed.