Features
- Packaged in 20-pin (150 mil) SSOP (QSOP)
- Available in Pb (lead) free package
- 12.5 MHz or 25 MHz fundamental crystal or clock input
- Six output clocks with selectable frequencies
- SDRAM frequencies of 67, 83, 100, and 133 MHz
- Buffered crystal reference output
- Zero ppm synthesis error in all clocks
- Ideal for PCM-Sierra's ATM switch chips
- Full CMOS output swing with 25 mA output drive capability at TTL levels
- Advanced, low-power, sub-micron CMOS process
- Operating voltage of 3.3 V
- Industrial temperature range only
Description
The IDT650-27 is a low cost, low-jitter, high-performance clock synthesizer for networking applications. Using analog Phase Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASIDT. The IDT650-27 outputs all have zero ppm synthesis error. The IDT650-27 is pin compatible and functionally equivalent to the IDT650-07. It is a performance upgrade and is recommended for all new 3.3 V designs. See the MK74CB214, IDT551, and IDT552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the IDT570, IDT9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.
Applied Filters: