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Low Phase Noise Clock Multiplier

Package Information

Pitch (mm) 0.65
Lead Count (#) 16
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Pkg. Code PGG16
Pkg. Type TSSOP

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

Product Attributes

Lead Count (#) 16
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Carrier (#) 0
Package Area (mm²) 22.0
Pitch (mm) 0.65
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Qty. per Reel (#) 2500
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range 0 to 70°C
Accepts Spread Spec Input Yes
Advanced Features Accepts Spread Spec Input, Reference Output
C-C Jitter Max P-P (ps) 18
Core Voltage (V) 3.3
Feedback Input No
Input Freq (MHz) 10 - 27
Input Type Crystal, LVCMOS
Inputs (#) 5
Length (mm) 5
MOQ 2500
Output Banks (#) 2
Output Freq Range (MHz) 0 - 156
Output Skew (ps) 250
Output Type LVCMOS
Output Voltage (V) 3.3, 5
Outputs (#) 2
Period Jitter Max P-P (ps) 75.000
Period Jitter Typ P-P (ps) 50.000
Pkg. Type TSSOP
Prog. Clock No
Reel Size (in) 13
Reference Output Yes
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Spread Spectrum No
Supply Voltage (V) 3.3 - 5
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4
Xtal Freq (KHz) 10 - 27
Xtal Inputs (#) 1

Description

The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is Renesas’ lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using Renesas’ patented analog and digital Phase-Locked Loop (PLL)  techniques, the chip accepts a 10 - 27 MHz crystal or clock input, and produces output clocks up to 156 MHz at 3.3 V. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. For applications which require defined input to output timing, use the ICS670-01.