Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG20 |
| Lead Count (#): | 20 |
| Pkg. Dimensions (mm): | 6.5 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Lead Count (#) | 20 |
| Carrier Type | Tube |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 74 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Accepts Spread Spec Input | No |
| Advanced Features | Spread Spectrum, Reference Output |
| App Jitter Compliance | MOST |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 21.5 - 21.5 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 9 |
| Length (mm) | 6.5 |
| MOQ | 2516 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 45.1584 - 45.1584, 49.152 - 49.152, 90.3168 - 90.3168, 98.304 - 98.304 |
| Output Signaling | CMOS, TTL |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 4 |
| Package Area (mm²) | 28.6 |
| Period Jitter Max P-P (ps) | 95 |
| Period Jitter Typ P-P (ps) | 45 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 6.5 x 4.4 x 1.0 |
| Pkg. Type | TSSOP |
| Platform Name | MOST |
| Product Category | General Purpose Clocks |
| Prog. Clock | No |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | No |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | No |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
| Xtal Freq (KHz) | 21.5 - 21.5 |
| Xtal Inputs (#) | 1 |
The 5V80001 is a high-performance clock interface for use in MOST® (Media Oriented Systems Transport) enabled systems. It can be used in two modes: generating a master clock for the ring, or performing clock/data recovery in a slave node.