Features
- 4 – 0.7V current mode differential HCSL output pairs
- Low additive jitter
- suitable for use in PCIe Gen2 and Gen3 systems
- 20-pin TSSOP package
- small board footprint
- Outputs can be terminated to LVDS
- can drive a wider variety of devices
- OE control pin
- greater system power management
- Industrial temperature range available
- supports demanding embedded applications
- Additive cycle-to-cycle jitter <5 ps
- Additive phase jitter (PCIe Gen2/3) <0.2ps
- Operating frequency up to 200MHz
5V41067A - Block Diagram
Description
The 5V41067A is a 2:4 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41067A selects between 1 of 2 differential HCSL inputs to fanout to 4 differential HCSL output pairs. The outputs can also be terminated to LVDS.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 5V41067APGG | Obsolete | N/A | In Stock | TSSOP | 20# | Tube | 1 | 0 | 74# | Yes | e3 Sn | 0 to 70°C |
| 5V41067APGG8 | Obsolete | N/A | Out of Stock | TSSOP | 20# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | 0 to 70°C |
| 5V41067APGGI | Obsolete | N/A | In Stock | TSSOP | 20# | Tube | 1 | 0 | 74# | Yes | e3 Sn | -40 to 85°C |
| 5V41067APGGI8 | Obsolete | N/A | Out of Stock | TSSOP | 20# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C |
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- End Of Life NoticePDF 859 KB Mar 24, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 120 KB 7WDXRDKU4E7E-5-57289 May 06, 2014
- Application NotePDF 160 KB 7WDXRDKU4E7E-5-57287 May 06, 2014
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (11)
Application Notes & White Papers (11)
- End Of Life NoticePDF 859 KB Mar 24, 2022
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015View More (7)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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