Features
- 2 - 0.7V current mode differential HCSL output pairs
- 16-pin TSSOP and VFQFPN package; small board footprint
- Spread-spectrum capable; reduces EMI
- Outputs can be terminated to LVDS; can drive a wider variety of devices
- 25 MHz, 125 MHz and 200 MHz output frequencies; supports Ethernet applications
- OE control pin; greater system power management
- Spread% and frequency pin selection; no software required to configure device
- Industrial temperature range available; supports demanding embedded applications
- For PCIe Gen3 applications, see the 5V41235
- Cycle-to-cycle jitter < 100 ps
- Output-to-output skew < 50 ps
- PCIe Gen2 phase jitter < 3.0ps RMS
5V41065 - Block Diagram
Description
The 5V41065 is a PCIe Gen2 compliant spread spectrum capable clock generator. The device has 2 differential HCSL outputs and can be used in communication or embedded systems to substantially reduce electro-magnetic interference (EMI). The spread amount and output frequency are selectable via select pins. The 5V41065 can also supply 25 MHz, 125 MHz and 200 MHz outputs for applications such as Ethernet.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 2 |
| Diff. Output Signaling | HCSL |
| Output Freq Range (MHz) | 25 - 25, 100 - 100, 125 - 125, 200 - 200 |
| Power Consumption Typ (mW) | 281 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | HCSL |
| Xtal Freq (MHz) | 25 - 25 |
| Diff. Termination Resistors | 8 |
| Package Area (mm²) | 9, 22 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3 |
| Product Category | PCI Express Clocks |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Carrier (#) | Package Area (mm²) | Pitch (mm) | Pkg. Dimensions (mm) | Qty. per Reel (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 5V41065NLG | Active | Available | In Stock | VFQFPN | 1ku | $1.9 | 16# | Tray | 3 | 624# | 9mm² | 0.5mm | 3.0 x 3.0 x 1.0 | 0 | Yes | e3 Sn | 0 to 70°C | MALAYSIA | SINGAPORE |
| 5V41065NLG8 | Active | N/A | Out of Stock | VFQFPN | 1ku | $1.9 | 16# | Reel | 3 | 0 | 9mm² | 0.5mm | 3.0 x 3.0 x 1.0 | 2500# | Yes | e3 Sn | 0 to 70°C | MALAYSIA | SINGAPORE |
| 5V41065NLGI | Active | Available | In Stock | VFQFPN | 1ku | $2.07 | 16# | Tray | 3 | 624# | 9mm² | 0.5mm | 3.0 x 3.0 x 1.0 | 0 | Yes | e3 Sn | -40 to 85°C | MALAYSIA | SINGAPORE |
| 5V41065NLGI8 | Active | N/A | Out of Stock | VFQFPN | 1ku | $2.07 | 16# | Reel | 3 | 0 | 9mm² | 0.5mm | 3.0 x 3.0 x 1.0 | 2500# | Yes | e3 Sn | -40 to 85°C | MALAYSIA | SINGAPORE |
| 5V41065PGG | Active | Available | In Stock | TSSOP | 1ku | $1.9 | 16# | Tube | 1 | 96# | 22mm² | 0.65mm | 5.0 x 4.4 x 1.0 | 0 | Yes | e3 Sn | 0 to 70°C | PHILIPPINES, TAIWAN | SINGAPORE |
| 5V41065PGG8 | Active | N/A | In Stock | TSSOP | 1ku | $1.9 | 16# | Reel | 1 | 0 | 22mm² | 0.65mm | 5.0 x 4.4 x 1.0 | 2500# | Yes | e3 Sn | 0 to 70°C | PHILIPPINES, TAIWAN | SINGAPORE |
| 5V41065PGGI | Active | Available | In Stock | TSSOP | 1ku | $2.07 | 16# | Tube | 1 | 96# | 22mm² | 0.65mm | 5.0 x 4.4 x 1.0 | 0 | Yes | e3 Sn | -40 to 85°C | PHILIPPINES, TAIWAN | SINGAPORE |
| 5V41065PGGI8 | Active | N/A | In Stock | TSSOP | 1ku | $2.07 | 16# | Reel | 1 | 0 | 22mm² | 0.65mm | 5.0 x 4.4 x 1.0 | 2500# | Yes | e3 Sn | -40 to 85°C | PHILIPPINES, TAIWAN | SINGAPORE |
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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