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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.

1-to-5 LVCMOS/LVTTL Fanout Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:TSSOP
Pkg. Code:PGG28
Lead Count (#):28
Pkg. Dimensions (mm):9.7 x 4.4 x 1.0
Pitch (mm):0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)28
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)50
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Core Voltage (V)2.5
FunctionBuffer
Input Freq (MHz)200
Input TypeLVCMOS, LVTTL
Inputs (#)1
Length (mm)9.7
MOQ250
Output Banks (#)1
Output Freq Range (MHz)200
Output SignalingLVCMOS
Output Skew (ps)25
Output TypeLVCMOS
Output Voltage (V)2.5V, 1.8V, 1.5V
Outputs (#)5
Package Area (mm²)42.7
Pitch (mm)0.65
Pkg. Dimensions (mm)9.7 x 4.4 x 1.0
Pkg. TypeTSSOP
Product CategoryClock Buffers & Drivers
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Thickness (mm)1
Width (mm)4.4

Description

The 5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise.