Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG8 |
| Lead Count (#): | 8 |
| Pkg. Dimensions (mm): | 3.1 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Lead Count (#) | 8 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| C-C Jitter Max P-P (ps) | 40 |
| Core Voltage (V) | 1.8 |
| Feedback Input | No |
| Input Freq (MHz) | 125 - 425 |
| Input Type | SSTL |
| Inputs (#) | 1 |
| Length (mm) | 3.1 |
| MOQ | 2500 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 125 - 425 |
| Output Type | SSTL |
| Output Voltage (V) | 1.8 |
| Outputs (#) | 1 |
| Package Area (mm²) | 13.6 |
| Period Jitter Max P-P (ps) | 40 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 3.1 x 4.4 x 1.0 |
| Pkg. Type | TSSOP |
| Product Category | Zero Delay Buffers |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
The IDT5P61006 is a low-cost, low voltage zero delay buffer for DDR2/800 applications. Using analog/digital Phase-Locked Loop techniques, the device accepts a 425 MHz clock input and provides a zero-delay output of the same frequency. The IDT5P61006 features an on-chip feedback circuit, eliminating the need for external feedback traces and components.