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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.

Zero Delay, Low Skew Buffer

Package Information

CAD Model:View CAD Model
Pkg. Type:SOIC
Pkg. Code:DCG8
Lead Count (#):8
Pkg. Dimensions (mm):4.9 x 3.9 x 1.5
Pitch (mm):1.27

Environmental & Export Classifications

Moisture Sensitivity Level (MSL)1
Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090

Product Attributes

Lead Count (#)8
Carrier TypeTube
Moisture Sensitivity Level (MSL)1
Qty. per Reel (#)0
Qty. per Carrier (#)97
Pb (Lead) FreeYes
Pb Free Categorye3 Sn
Temp. Range (°C)-40 to 85°C
Advanced FeaturesFeedback Input, Spread Spectrum
C-C Jitter Max P-P (ps)250
Core Voltage (V)3.3V, 5V
Feedback InputYes
Input Freq (MHz)20 - 160
Input TypeLVCMOS
Inputs (#)1
Length (mm)4.9
MOQ194
Output Banks (#)1
Output Freq Range (MHz)20 - 160
Output Skew (ps)150
Output TypeLVCMOS
Output Voltage (V)3.3V, 5V
Outputs (#)4
Package Area (mm²)19.1
Period Jitter Typ P-P (ps)170
Pitch (mm)1.27
Pkg. Dimensions (mm)4.9 x 3.9 x 1.5
Pkg. TypeSOIC
Price (USD)$17.86974
Product CategoryZero Delay Buffers
Prog. ClockNo
Reference OutputNo
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Spread SpectrumYes
Tape & ReelNo
Thickness (mm)1.5
Width (mm)3.9

Description

The 574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.