Features
- Packaged in 20-pin TSSOP
- Pb (lead) free packaging
- Operating voltage of 3.3 V
- Low power consumption
- Input differential clock of up to 200 MHz
- Jitter 60 ps (cycle-to-cycle)
- Output-to-output skew of 50 ps
- Available in industrial temperature range (-40 to +85°C)
- For PCIe Gen2/3 applications, see the 5V41067A
557-06 - Block Diagram
Description
The 557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential HCSL input pairs and fans out to four pairs of differential HCSL or LVDS outputs.
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 557G-06LF | NRND | N/A | In Stock | TSSOP | 1ku | $2.28 | 20# | Tube | 1 | 0 | 74# | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 557G-06LFT | NRND | N/A | Out of Stock | TSSOP | 1ku | $2.28 | 20# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 557GI-06LF | NRND | N/A | Out of Stock | TSSOP | 1ku | $2.54 | 20# | Tube | 1 | 0 | 74# | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
| 557GI-06LFT | NRND | N/A | In Stock | TSSOP | 1ku | $2.54 | 20# | Reel | 1 | 3000# | 0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Application NotePDF 160 KB 7WDXRDKU4E7E-5-57287 May 06, 2014
- Product Change NoticePDF 361 KB 7WDXRDKU4E7E-5-55130 Mar 24, 2013
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014View More (11)
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- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-60321 Apr 14, 2016
- Product Change NoticePDF 611 KB 7WDXRDKU4E7E-5-59927 Feb 15, 2016
- Product Change NoticePDF 596 KB 7WDXRDKU4E7E-5-59884 Jan 28, 2016
- Product Change NoticePDF 544 KB 7WDXRDKU4E7E-5-59710 Nov 13, 2015
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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