Features
- Packaged in 16-pin TSSOP
- RoHS 5 (green) or RoHS 6 (green and lead free) compliant packaging
- Supports HCSL or LVDS output levels
- Operating voltage of 3.3 V
- Input frequency of 25 MHz
- Jitter 60 ps (cycle-to-cycle)
- Spread Spectrum capability
- Industrial and commercial temperature ranges
- For PCIe Gen2 applications, see the 5V41065
- For PCIe Gen3 applications, see the 5V41235
557-03 - Block Diagram
Description
The 557-03 is a spread spectrum clock generator that supports PCI-Express Gen 1 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. The spread type and amount are configured via select pin. Using IDT's patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.
Parameters
| Attributes | Value |
|---|---|
| Diff. Outputs | 2 |
| Diff. Output Signaling | HCSL |
| Output Freq Range (MHz) | 25 - 25, 100 - 100, 125 - 125, 200 - 200 |
| Power Consumption Typ (mW) | 257 |
| Supply Voltage (V) | 3.3 - 3.3 |
| Output Type | HCSL |
| Xtal Freq (MHz) | 25 - 25 |
| Diff. Termination Resistors | 8 |
| Package Area (mm²) | 22 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 25 - 25 |
| Input Type | Crystal, LVCMOS |
| Output Banks (#) | 1 |
| Core Voltage (V) | 3.3 |
| Output Voltage (V) | 3.3 |
| Product Category | PCI Express Clocks |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| TSSOP | 5.0 x 4.4 x 1.0 | 16 | 0.65 |
| Part Number | Status | Samples | Stock | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 557G-03LF | Active | Available | In Stock | TSSOP | 1ku | $1.56 | 16# | Tube | 1 | 0 | 96# | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 557G-03LFT | Active | N/A | In Stock | TSSOP | 1ku | $1.56 | 16# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C | TAIWAN | SINGAPORE |
| 557GI-03LF | Active | Available | In Stock | TSSOP | 1ku | $1.69 | 16# | Tube | 1 | 0 | 96# | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
| 557GI-03LFT | Active | N/A | In Stock | TSSOP | 1ku | $1.69 | 16# | Reel | 1 | 2500# | 0 | Yes | e3 Sn | -40 to 85°C | TAIWAN | SINGAPORE |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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