Features
- Low additive phase jitter RMS: 50fs
- Extremely low skew outputs (50ps)
- Low-cost clock buffer
- Packaged in 8-pin SOIC and small 8-pin DFN packages, Pb-free
- Input/Output clock frequency up to 200MHz
- Ideal for networking clocks
- Operating voltages: 1.8V to 3.3V
- Output Enable mode tri-state outputs
- Advanced, low-power CMOS process
- Extended temperature range: -40 °C to +105 °C
553S Block Diagram
Description
The 553S is a low skew, single input to four output, LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.
Parameters
| Attributes | Value |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers |
Support Communities
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alternate of Infineon part CY7B9910-5SXI
Currently, we are looking for an alternate of discontinued Infineon part CY7B9910-5SXI.This is Low Skew Clock Buffer 80MHz-OUT 24-Pin SOIC. Kindly let me know the nearest alternate.
Mar 3, 2026 -
What is the difference between theses 1 to 4 LVCMOS buffers?
What is the difference between the following 1 to 4 LVCMOS buffers: 553S, 551S, 651S, 621S & 524S, 74FCT38074S and 5PB1104?
Apr 23, 2024
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