Features
- Pin and function compatible to Cypress W180-52
- Packaged in 8-pin SOIC
- Provides a spread spectrum output clock
- Accepts a clock input and provides same frequency dithered output
- Input frequency of 8 to 15 MHz
- Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics
- Spread percentage selection for +/-0.625% and +/-1.875%
- Operating voltage of 3.3 V and 5 V
- Advanced, low-power CMOS process
180-52 - Block Diagram
Description
The 180-52 generates a low EMI output clock from a clock or crystal input. The device uses IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The 180-52 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. IDT offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.
Support Communities
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Build error: RA4M2
... SCKDIVCR' 1056 | R_SYSTEM->SCKDIVCR = BSP_PRV_STARTUP_SCKDIVCR; | ^~~~~~~~~~~~~~~~~~~~~~~~ ../ra/fsp/src/bsp/mcu/all/bsp_clocks.c:180:52: error: 'BSP_CFG_FCLK_DIV' undeclared (first use in this function) 180 | #define BSP_PRV_STARTUP_SCKDIVCR_FCLK_BITS ((BSP_CFG_FCLK ...
Jul 24, 2024
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