Package Information
| Lead Count (#) | 24 |
| Pkg. Type | SOIC |
| Pkg. Code | PSG24 |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 15.4 x 7.6 x 2.34 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390000 |
| Moisture Sensitivity Level (MSL) | 1 |
Product Attributes
| Pkg. Type | SOIC |
| Lead Count (#) | 24 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| Advanced Features | Programmable Clock, Feedback Input |
| Core Voltage (V) | 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 0.015734 - 100 |
| Input Type | LVCMOS |
| Inputs (#) | 2 |
| Length (mm) | 15.4 |
| MOQ | 62 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 5 |
| Output Freq Range (MHz) | 0 - 250 |
| Output Type | LVPECL, SSTL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 5 |
| Package Area (mm²) | 117.0 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 15.4 x 7.6 x 2.34 |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Qty. per Carrier (#) | 31 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range | 0 to 70°C |
| Thickness (mm) | 2.34 |
| Width (mm) | 7.6 |
Description
The 1523 is a low-cost, high-performance frequency generator. It is well suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using IDT's advanced low-voltage CMOS mixed-mode technology, the 1523 is an effective phase controlled clock synthesizer and also supports video projectors and displays at resolutions from VGA to beyond UXGA. The 1523 offers clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. Dynamic Phase Adjust (DPA) allows I2C™ control of the output clock's phase relative to the input sync signal. A second, half speed set of outputs that can be separately enabled allows such applications as clocking analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output, or the input HSYNC after being sharpened by the Schmitt trigger. Both signals are then delayed by the DPA. The advanced PLL uses either its internal programmable feedback divider or an external divider. Either the internal or external loop filters is software selectable. The COAST input pin disables the PLL's charge pump, causing the device to idle at the current speed for short periods of time, such as vertical blanking intervals. The device is programmed by a standard I2C-bus serial interface and is available in a 24-pin, wide small-outline integrated circuit (SOIC) package.