Overview
Description
The SH7211 is a high-end single chip microcontroller with on-chip flash memory, which incorporates an SH-2A core and achieves operation of 160MHz. TheSH-2A CPU core employs a superscalar architecture enabling simultaneous execution of two instructions. Compared with the conventional SH-1 andSH-2, a tremendous increase in processing performance is realized. The SH7211 incorporates register banks. When an interrupt event occurs, CPU internal register information is stored in registers at high speed. This make it possible to improve real-time control performance greatly. This LSI includes abundant peripheral functions suited f or industrial applications, such as a multifunction timer unit 12-bit A/D converter and 8-bit D/A converter.
Comparison
Applications
Design & Development
Software & Tools
Sample Code
Boards & Kits
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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Support Communities
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max. speed of DMAC SH7211
Looking at datasheet of SH7211, there are three access cycles to get response from external SRAM to external device using DREQ1 und DTACK1 in single address mode. Two cycles are used by CPU and the third cycle should deliver requested data. I set all idle and wait states to 0 ...
Apr 17, 2009 -
SH-2A 7211 question
I am looking SH7211 hardware manual encountered a problem. Why SH7211 hardware manual 3.4 Chapter on-chip peripheral I / O registers map address is H'FFFFC000-H'FFFFFF, while the 26.1 chapter register addresse is H'FFFC000?
Nov 27, 2009 -
Dhrystone MIPS for SH7216
http://am.renesas.com/products/mpumcu/superh/sh7216/sh7216_landing.jsp claims 2.0DMIPS per MHZ for SH7216.I have not been able to achieve that using the SH7216 RSK.Does anyone know the settings (compiler settings, memory layout etc) used to generate ...
Apr 21, 2011
FAQs
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How to write to the internal flash memory with the MCU in boot mode?
Please check the following points. ・Power-on reset is correct. ‐Reset signal is cleared after the oscillation is stabilized at the time of power-on. ‐The hardware stand-by pin (HSTBY) is not switched to Low at power-on if your MCU has a stand-by function. ・The mode pin ...
Sep 9, 2011 -
What will happen if TFRST and RFRST in SCFCR of SCIF with FIFO is set to 1?
When TFRST is 1, the transmit FIFO data register (SCFTDR) is reset, however, the transmit shift register (SCTSR) continues the operation. Therefore the transmit data that has already been transferred to the SCTSR will be transmitted. When RFRST is 1, the receive FIFO data register (SCFERDR) is reset, but the ...
Mar 21, 2012 -
Is fractional portion 0.5 cycle equivalent to standard value 1/2tcyc?
2 cycles are added to the Th when 10:2.5 cycle is set to the SW[1:0] bit, and 2 cycles are added to the Tf when 10:2.5 cycle is set to the HW[1:0] bit. As you mentioned.
Sep 11, 2012