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V850ES/SG2, V850ES/SJ2(Non Promotion)

The V850ES/SG2 and V850ES/SJ2 is supported only for the customers who have already adopted any of the products. For new adoption, please consider V850ES/Sx3 or RH850/F1L products.

 

Main Solutions

Key Features:

  • Operating Voltage: 3.0 to 3.6 V
  • Max. frequency: 20 MHz
  • ROM capacities: 256 KB to 640 KB mask ROM and 384 KB to 640 KB flash memory
  • RAM capacities: 24 KB to 48 KB
  • Package: 100-pin plastic QFP, 144-pin plastic QFP
  • Minimum instruction execution time: 50 ns (operating with main clock (fXX) = 20 MHz)
  • General-purpose registers: 32 bits x 32 registers
  • CPU features:
    • Signed multiplication (16 x 16 -> 32): 1 to 2 clocks
    • Signed multiplication (32 x 32 -> 64): 1 to 5 clocks
    • Saturated operations (overflow and underflow detection functions included)
    • 32-bit shift instruction: 1 clock
    • Bit manipulation instructions
    • Load/store instructions with long/short format
  • Memory space:
    • 64 MB of linear address space (for programs and data)
    • External expansion: Up to 4 MB
  • External bus interface:
    • Separate bus/multiplexed bus output selectable
    • 8/16 bit data bus sizing function
    • Wait function (Programmable wait function, External wait function)
    • Idle state function
    • Bus hold function
  • Interrupts and exceptions:
    • Non-maskable interrupts: 2 sources
    • Maskable interrupts: 54/55/58/59/60/63/64/67/68 sources
    • Software exceptions: 32 sources
    • Exception trap: 2 sources
  • I/O ports: 84
  • Timer function:
    • 16-bit interval timer M (TMM): 1 channel
    • 16-bit timer/event counter P (TMP): 6/9 channels
    • 16-bit timer/event counter Q (TMQ): 1 channel
    • Watch timer: 1 channel
    • Watchdog timer: 1 channel
  • Real-time output port: 6 bits x 1/2 channel
  • Serial interface:
    • Asynchronous serial interface A (UARTA)
    • 3-wire variable-length serial interface B (CSIB)
    • I2C bus interface (I2C) (I2C bus versions (Y products) only)
    • UARTA/CSIB: 1 channel
    • UARTA/I2C: 2 channels
    • CSIB/I2C: 1 channel
    • CSIB: 3/4 channels
    • UARTA: 0/1 channel
  • IEBus controller: 1 channel (IEBus controller version only)
  • CAN controller: 1 channel (CAN controller version only)
  • A/D converter: 10-bit resolution: 12/16 channels
  • D/A converter: 8-bit resolution: 2 channels
  • DMA controller: 4 channels
  • CRC function: 16-bit error detection codes are generated for data in 8-bit units
  • On-chip debug function: JTAG interface (flash memory version only)
  • ROM correction: 4 correction addresses specifiable
  • Clock generator:
    • During main clock or subclock operation
    • 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
    • Clock-through mode/PLL mode selectable
  • Internal oscillation clock: 200 kHz (TYP.)
  • Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode

 

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You can find technical updates and datasheets for this product here.
You can find an explanation of orderable part numbers here.

Resources for Software and Hardware

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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