The ADC1412D125HN is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signaling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. The device also includes a programmable gain amplifier with a flexible input voltage range.

特長

  • CMOS or LVDS DDR digital outputs
  • Dual-channel14-bit pipelined ADC core
  • Duty cycle stabilizer
  • Fast OTR detection
  • Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine
  • gain
  • INL &plusmn
  • 1 LSB, DNL &plusmn
  • 0.5 LSB (typical)
  • Input bandwidth, 650 MHz
  • Offset binary, 2's complement, gray code
  • Power dissipation, 775 mW at 80 Msps
  • Power-down and Sleep modes
  • Sample rate up to 125 Msps
  • SFDR, 90 dBc
  • Single 3 V supply
  • SNR, 73 dB
  • SPI Interface

製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete VFQFPN 64 I はい Tray
Availability
Obsolete VFQFPN 64 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル language 分類 形式 サイズ 日付
データシート
ADC1412D SER Datasheet データシート PDF 600 KB
PCN / PDN
PDN# : DC-14-07 PRODUCT DISCONTINUANCE NOTICE 製品中止通知 PDF 528 KB

ボード&キット

製品名 タイトル 分類 Company
ADC1412D125F1 ADC1412D125F1 demo board; CMOS version; SPI, Regulators and CMOS buffer on board デモ Renesas
ADC1412D125F2 ADC1412D125F2 demo board; LVDS version; SPI, Regulators and LVDS outputs on board デモ Renesas