20-Output DB2000Q PCIe Clock Buffer
Jump to Page Section:
Overview
Description
The 9QXL2000B is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen4 and Gen5. It offers integrated terminations for 85Ω transmission lines with individual output impedance trim and via SMBus registers.
Features
- Low-Power HCSL (LP-HCSL) 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
- Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
- 8 OE# pins configurable to control up to 20 outputs
- 9 selectable SMBus addresses
- Spread spectrum compatible
- 10 × 10 mm 72-VFQFPN package
Documentation
| Title | Type | Date | |
|---|---|---|---|
PDF320 KB
|
Datasheet
|
||
PDF91 KB
|
Application Note
|
||
PDF1.99 MB
|
Application Note
|
||
PDF255 KB
|
Application Note
|
||
PDF322 KB
|
Application Note
|
||
PDF480 KB
|
Application Note
|
||
PDF235 KB
|
Application Note
|
||
PDF170 KB
|
Application Note
|
||
PDF495 KB
|
Application Note
|
||
PDF442 KB
|
Application Note
|
||
PDF160 KB
|
Application Note
|
||
PDF120 KB
|
Application Note
|
||
PDF565 KB
|
Application Note
|
||
PDF137 KB
|
Application Note
|
||
PDF2.40 MB
|
Overview
|
||
PDF1.83 MB
|
Overview
|
||
PDF145 KB
|
Product Change Notice
|
||
PDF983 KB
|
Product Change Notice
|
||
PDF101 KB
|
Schematic
|
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
Processing table
| VFQFPN | 72 | I | Yes | Tray | Get Samples, | |
| VFQFPN | 72 | I | Yes | Reel |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
play_circle_filledVideos & Training
PCIe Gen5 Clock Buffers
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.
Video List