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4:2 Differential-to-LVPECL/LVDS Clock Multiplexer

Package Information

CAD Model: View CAD Model
Pkg. Type: TSSOP
Pkg. Code: PGG20
Lead Count (#): 20
Pkg. Dimensions (mm): 6.5 x 4.4 x 1.0
Pitch (mm): 0.65

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) EAR99
HTS (US) 8542.39.0090

Product Attributes

Lead Count (#) 20
Carrier Type Reel
Moisture Sensitivity Level (MSL) 1
Qty. per Reel (#) 3000
Qty. per Carrier (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range (°C) -40 to 85°C
Additive Phase Jitter Typ RMS (fs) 22
Additive Phase Jitter Typ RMS (ps) 0.022
Adjustable Phase No
Advanced Features Universal outputs
Channels (#) 1
Core Voltage (V) 2.5V, 3.3V
Function Buffer, Multiplexer
Input Freq (MHz) 3000
Input Type CML, LVDS, LVPECL, SSTL
Inputs (#) 4
Length (mm) 6.5
MOQ 3000
Output Banks (#) 1
Output Freq Range (MHz) 3000
Output Skew (ps) 25
Output Type LVDS, LVPECL
Output Voltage (V) 2.5V, 3.3V
Outputs (#) 2
Package Area (mm²) 28.6
Pitch (mm) 0.65
Pkg. Dimensions (mm) 6.5 x 4.4 x 1.0
Pkg. Type TSSOP
Prog. Interface Pin select
Published No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Supply Voltage (V) 2.5 - 2.5, 3.3 - 3.3
Tape & Reel Yes
Thickness (mm) 1
Width (mm) 4.4

Description

The 859S0412I is a 4:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The 859S0412I has 4 selectable differential PCLKx/nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The clock select pins have internal pulldown resistors. The CLK_SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).