Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG16 |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 5.0 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 1 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
Product Attributes
| Lead Count (#) | 16 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 1 |
| Qty. per Reel (#) | 2500 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | 0 to 70°C |
| Accepts Spread Spec Input | Yes |
| Additive Phase Jitter Typ RMS (fs) | 100 |
| Additive Phase Jitter Typ RMS (ps) | 0.1 |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3 |
| Architecture | Common, SRNS |
| C-C Jitter Max P-P (ps) | 100 |
| Core Voltage (V) | 3.3 |
| Diff. Input Signaling | HCSL |
| Diff. Inputs | 2 |
| Diff. Output Signaling | HCSL |
| Diff. Outputs | 1 |
| Diff. Termination Resistors | 4 |
| Function | Mulitplexer |
| Input Freq (MHz) | 25 - 25 |
| Input Type | HCSL |
| Length (mm) | 5 |
| MOQ | 2500 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 200 |
| Output Skew (ps) | 50 |
| Output Type | HCSL |
| Output Voltage (V) | 0.8 |
| Outputs (#) | 1 |
| PLL | Yes |
| Package Area (mm²) | 22 |
| Phase Jitter Max RMS (ps) | 2.2 |
| Phase Jitter Typ RMS (ps) | 1.9 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 5.0 x 4.4 x 1.0 |
| Pkg. Type | TSSOP |
| Power Consumption Typ (mW) | 132 |
| Product Category | PCI Express Clocks |
| Prog. Clock | No |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
| Xtal Inputs (#) | 1 |
Resources for 6V31023
Description
The 6V31023 is a 2:1 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 6V31023 selects between 1 of 2 differential HCSL inputs to drive a single differential HCSL output pair. The output can also be terminated to LVDS.
