Package Information
| Pkg. Type: | TQFP |
| Pkg. Code: | PRG32 |
| Lead Count (#): | 32 |
| Pkg. Dimensions (mm): | 7.0 x 7.0 x 1.4 |
| Pitch (mm): | 0.8 |
Environmental & Export Classifications
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
Product Attributes
| Pkg. Type | TQFP |
| Lead Count (#) | 32 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tray |
| C-C Jitter Max P-P (ps) | 100 |
| Core Voltage (V) | 2.5 |
| Divider Value | 1, 2, 3, 4, 5, 6, 8, 10, 12 |
| Function | Buffer |
| Input Freq (MHz) | 6 - 200 |
| Input Type | LVCMOS, LVTTL |
| Inputs (#) | 1 |
| Length (mm) | 7 |
| MOQ | 125 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 2 |
| Output Freq Range (MHz) | 200 - 200 |
| Output Signaling | LVCMOS, LVTTL |
| Output Skew (ps) | 185 |
| Output Type | LVCMOS, LVTTL |
| Output Voltage (V) | 2.5 |
| Outputs (#) | 8 |
| Package Area (mm²) | 49 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
| Published | No |
| Qty. per Carrier (#) | 250 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | -40 to 85°C |
| Thickness (mm) | 1.4 |
| VCO Max Freq (MHz) | 200 |
| VCO Min Freq (MHz) | 24 |
| Width (mm) | 7 |
Resources for 5T9950A
Description
The 5T9950 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The 5T9950 has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. The LOCK output asserts to indicate when Phase Lock has been achieved. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The 5T9950 has LVTTL outputs with 12mA balanced drive outputs.