Renesas’ Timing product portfolio has been acquired by SiTime.
Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to SalesClocks@sitime.com. Full transition to SiTime is expected by late 2026.
| CAD Model: | View CAD Model |
| Pkg. Type: | TSSOP |
| Pkg. Code: | PGG16 |
| Lead Count (#): | 16 |
| Pkg. Dimensions (mm): | 5.0 x 4.4 x 1.0 |
| Pitch (mm): | 0.65 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 1 |
| Pkg. Type | TSSOP |
| Lead Count (#) | 16 |
| Pb (Lead) Free | Yes |
| Carrier Type | Reel |
| Advanced Features | Programmable Clock |
| Core Voltage (V) | 3.3 |
| Feedback Input | No |
| Input Freq (MHz) | 3.0E-5 - 0.00012, 0.008 - 10, 0.02 - 100 |
| Input Type | LVCMOS |
| Inputs (#) | 3 |
| Length (mm) | 5 |
| MOQ | 2500 |
| Moisture Sensitivity Level (MSL) | 1 |
| Output Banks (#) | 3 |
| Output Freq Range (MHz) | 2.5 - 110 |
| Output Skew (ps) | 1000 |
| Output Type | LVCMOS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 3 |
| Package Area (mm²) | 22 |
| Pb Free Category | e3 Sn |
| Period Jitter Typ P-P (ps) | 200 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 5.0 x 4.4 x 1.0 |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Qty. per Carrier (#) | 0 |
| Qty. per Reel (#) | 2500 |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | Yes |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 1 |
| Width (mm) | 4.4 |
The 1526 is a low-cost, high-performance frequency generator. It is suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using IDT's advanced low-voltage CMOS mixed-mode technology, the 1526 is an effective clock synthesizer that supports video projectors and displays at resolutions from VGA to beyond XGA. The 1526 offers single-ended clock outputs to 110 MHz. The HSYNC_out, and VSYNC_out pins provide the regenerated versions of the HSYNC and VSYNC inputs synchronous to the CLK output. The advanced PLL uses its internal programmable feedback divider. The device is programmed by a standard I2C-bus™ serial interface and is available in a TSSOP16 package.