Overview

Description

The 71256 5V CMOS SRAM is organized as 32K x 8. The circuit also offers a reduced power standby mode for significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Military grade product is available.

Features

  • High-speed address/chip select time – Military: 25/35/45/55/70/85/100ns (max.) 
  • Commercial/Industrial: 20/25/35ns (max.) low power only
  • Low-power operation
  • Battery Backup operation – 2V data retention
  • Input and output directly TTL-compatible
  • Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (300 mil) SOJ
  • Military product compliant to MIL-STD-883, Class B

Documentation

Type
Date
PDF 249 KB Datasheet
PDF 471 KB 日本語 Guide
PDF 1.11 MB End Of Life Notice
PDF 1.27 MB 日本語 Guide
PDF 1.29 MB End Of Life Notice
PDF 1.22 MB End Of Life Notice
PDF 1.15 MB End Of Life Notice
PDF 938 KB End Of Life Notice
PDF 909 KB End Of Life Notice
PDF 748 KB Product Change Notice
PDF 108 KB Product Change Notice
PDF 27 KB Product Change Notice
PDF 24 KB Product Change Notice
PDF 68 KB Product Change Notice
14 items

Design & Development

Software & Tools

Software Downloads

Type
Date
PDF 1.11 MB End Of Life Notice
PDF 1.29 MB End Of Life Notice
PDF 1.22 MB End Of Life Notice
PDF 1.15 MB End Of Life Notice
PDF 938 KB End Of Life Notice
PDF 909 KB End Of Life Notice
6 items

Models