Features
- Generates up to four independent output frequencies with a total of 7 differential outputs and one reference LVCMOS output
- Supports multiple differential output I/O standards:
- Three universal output pairs with each configurable as one differential output pair (LVDS, LVPECL, or regular HCSL) or two LVCMOS outputs. The frequency of each output pair can be individually programmed
- Four copies of Low Power HCSL (LP-HCSL) outputs
- Meets PCIe® Gen 1/2/3, USB 3.0, 1/10 GbE clock requirements
- <0.7ps RMS typical phase jitter on outputs
- Four fractional output dividers (FODs)
- Independent spread spectrum capability from each fractional output divider
- Stores 4 different configurations in OTP non-volatile memory
- Input frequency ranges up to 200MHz
- Output frequency ranges up to 350MHz
- Programmable loop bandwidth and crystal load capacitance
- 1.8V/2.5V/3.3V core and output voltages
- Supported by the Timing Commander™ software tool
Description
The 5P49V5907 is a programmable clock generator intended for high-performance consumer, networking, industrial, computing, and data communications applications. Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using the I2C interface. This is Renesas' fifth generation of programmable clock technology (VersaClock® 5). The frequencies are generated from a single reference clock or crystal.
Two select pins allow up to four different configurations to be programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for different operating modes (full function, partial function, partial power down), regional standards (US, Japan, Europe), or system production margin testing. The device may be configured to use one of two I2C addresses to allow multiple devices to be used in a system. The device is packaged in a 40-pin 5mm x 5mm VFQFPN (NDG40), with an industrial operating temperature of -40 °C to +85 °C.
Applications
- Ethernet switch/router
- PCI Express 1.0/2.0/3.0
- Broadcast video/audio timing
- Multi-function printer
- Processor and FPGA clocking
- Any-frequency clock conversion
- MSAN/DSLAM/PON
- Fiber Channel, SAN
- Telecom line cards
- 1GbE and 10GbE
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Software & Tools
Sample Code
Simulation Models
This video provides an overview of IDT's programmable clock generators 5P49V5907 and 5P49V5908 featuring the fifth generation of programmable clock technology (VersaClock® 5). With additional outputs supporting PCI Express® timing, these devices present a blend of low power, flexibility, and high performance suitable for a wide range of applications including performance consumer, networking, industrial, computing, and data communications. For more information, visit the Programmable Clocks page.
Lab demonstration and clock jitter measurement showing VersaClock 5. The frequency analyzer shows phase jitter at approximately 575 picoseconds RMS. Presented by Baljit Chandhoke, product manager at IDT. For more information visit the Programmable Clocks page.
This video will show you how to program VersaClock® 5 Low Power Programmable Clock Generator.
Description
IDT's innovative support tool, Timing Commander™, expedites development cycles by empowering customers to program sophisticated timing devices with an intuitive and flexible Graphical User Interface. IDT's Timing Commander is a Windows™-based platform designed to serve user-friendly configuration interfaces, known as personalities, for various IDT products and product families. With a few simple clicks, the user is presented with a comprehensive, interactive block diagram offering the ability to modify desired input values, output values, and other configuration settings. The software automatically makes calculations, reports status monitors, and prepares register settings without the need to reference a datasheet. The tool also automatically loads the configuration settings over USB to an IDT evaluation board for immediate application in the circuit. Once the device has been configured and tuned for optimal system performance, the configuration file can be saved for factory-level programming before shipment. For more information about Timing Commander, visit our Timing Commander page.
Resources
IDT (acquired by Renesas) engineer provides a brief tutorial describing the main differences between standard HCSL and low-power HCSL (LP-HCSL).
Presented by Ron Wade, PCI Express timing expert.
Related Resources