The 8T49N012 is a high performance Clock Generator with selectable LVPECL or Single-ended outputs. The 8T49N012 can generate selectable frequencies from a crystal or a single-ended reference clock. The frequency is selected from the Frequency Selection Table.
 
Excellent phase noise performance is maintained with IDT’s Fourth Generation FemtoClock® NG PLL technology.

Features

  • Fourth Generation FemtoClock NG PLL technology
  • Three differential output banks:
    Bank A: selectable between four pairs of LVPECL or four pairs
                  of complementary LVCMOS/LVTTL outputs
    Bank B: two pairs of LVPECL outputs
    Bank C: six pairs of LVPECL outputs
  • Selectable clock input or crystal input.
  • Supports 25MHz fundamental crystal or 25MHz, 50MHz,
    66.67MHz clock input
  • Selectable 156.25MHz, 125MHz, 100MHz clock for Bank B and
    Bank C outputs
  • Selectable 156.25MHz, 125MHz, 100MHz, 250MHz, 312.5MHz,
    50MHz, 25MHz, 62.5MHz or 78.125MHz for Bank A outputs
  • PLL lock indication (LVCMOS output)
  • RMS phase jitter at 156.25MHz (12kHz - 20MHz): 0.199ps (typical)
  • Power supply modes:
    Core / Output
    3.3V / 3.3V
    3.3V / 2.5V
    2.5V / 2.5V
  • -40°C to 85°C ambient operating temperature
  • 56-Lead VFQFN
  • Lead-free (RoHS 6) packaging

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 56 I Yes Tray
Availability
Active VFQFPN 56 I Yes Reel
Availability

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
8T49N012 Datasheet Datasheet PDF 751 KB
User Guides & Manuals
Programmable FemtoClock Ordering Product Information Manual PDF 140 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-837 Overdriving the Crystal Interface Application Note PDF 133 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products Application Note PDF 108 KB
PCNs & PDNs
PCN# : A2005-01(R1) Add UTL, Thailand and JCET, China as Alternate Assembly Locations Product Change Notice PDF 725 KB
PCN# : A2005-01 Add UTL, Thailand and JCET, China as Alternate Assembly Locations Product Change Notice PDF 116 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
Other
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB