The 87322BI is a low skew, ÷1/÷2 3.3V LVPECL/ECL Clock Generator. Using multiplexed/redundant clock inputs the 87322BI is designed to translate most differential signal levels to LVPECL/ECL levels. The CLK_SEL input selects between CLK0, nCLK0 and CLK1, nCLK1 as the active input. The divide select inputs, DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input can be used to reset the internal dividers and disable the clock outputs. Disabled outputs QAx, QBx, QCx and QDx will be forced low. Disabled outputs nQAx, nQBx, nQCx and nQDx will be forced high. The 87322BI is characterized across the industrial temperature range and over the supply voltage range of 3V to 3.8V for LVPECL and -3.8V to -3V for LVECL/ECL. Guaranteed output and part to part skew characteristics make the 87322BI an excellent choice for clock generator and clock distribution applications demanding well defined performance and repeatability.


  • Fifteen differential LVPECL outputs
  • Selectable LVPECL differential clock inputs
  • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
  • Output frequency: 750MHz (maximum)
  • Output skew: 180ps (maximum)
  • Bank skew: 65ps (maximum)
  • Part-to-part skew: 500ps (maximum)
  • LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -3V
  • -40°C to 85°C ambient operating temperature
  • Lead-Free package fully RoHS compliant

Product Options

Orderable Part ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete 52 I Yes Tray
Obsolete 52 I Yes Reel

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
ICS87322BI Data Sheet Datasheet PDF 322 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PDN# : CQ-16-02 Quarter PDN for Declined Market Product Discontinuation Notice PDF 592 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB
Clock Distribution Overview 日本語 Overview PDF 217 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB