The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec.

Features

  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low cost clock buffer
  • Packaged in 8-SOIC and 8-DFN, Pb-free
  • Input / Output clock frequency up to 200MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating voltages: 1.8V to 3.3V
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active COL 8 I Yes Cut Tape
Availability
Active COL 8 I Yes Reel
Availability
Active SOIC 8 I Yes Tube
Availability
Active SOIC 8 I Yes Reel
Availability

Documentation

Title language Type Format File Size Date
Datasheets & Errata
524S Datasheet Datasheet PDF 263 KB
Application Notes & White Papers
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
PCNs & PDNs
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets Product Change Notice PDF 268 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB

Downloads

Title language Type Format File Size Date
Models
524S IBIS Model Model - IBIS ZIP 24 KB