524S - Low Skew 1 to 4 Clock Buffer

The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec.

Features

Part Number	Part Status	Pkg. Type	Lead Count (#)	Temp. Grade	Pb (Lead) Free	Carrier Type	Buy Sample
524SCMGI Package Info PCB Symbol, Footprint, and 3D Model	Active	COL	8	I	Yes	Cut Tape	Availability Buy / Quote
524SCMGI8 Package Info PCB Symbol, Footprint, and 3D Model	Active	COL	8	I	Yes	Reel	Availability Buy / Quote
524SDCGI Package Info PCB Symbol, Footprint, and 3D Model	Active	SOIC	8	I	Yes	Tube	Availability Buy / Quote
524SDCGI8 Package Info PCB Symbol, Footprint, and 3D Model	Active	SOIC	8	I	Yes	Reel	Availability Buy / Quote

	Title		Type	Format	File Size	Date
Datasheets & Errata
	524S Datasheet	–	Datasheet	PDF	263 KB	Mar 19, 2015
Application Notes & White Papers
	AN-845 Termination - LVCMOS	–	Application Note	PDF	146 KB	May 13, 2014
	AN-842 Thermal Considerations in Package Design and Selection	–	Application Note	PDF	495 KB	May 12, 2014
	AN-840 Jitter Specifications for Timing Signals	–	Application Note	PDF	442 KB	May 8, 2014
	AN-815 Understanding Jitter Units	–	Application Note	PDF	565 KB	Apr 24, 2014
PCNs & PDNs
	PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets	–	Product Change Notice	PDF	268 KB	Jun 12, 2019
	PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly	–	Product Change Notice	PDF	611 KB	Apr 13, 2016
	PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly	–	Product Change Notice	PDF	611 KB	Feb 14, 2016
Other
	Clock Distribution Overview	日本語	Overview	PDF	217 KB	Nov 6, 2020
	IDT Clock Generation Overview	日本語	Overview	PDF	1.83 MB	Apr 28, 2016