The 9DBL0641 6-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0641 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.
 
For information regarding evaluation boards and material, please contact your local sales representative.

Features

  • Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)
  • PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode)
  • 6 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
  • Direct connection to 100Ω transmission lines
  • Dedicated OE# pin for each output
  • Spread Spectrum tolerant
  • Pin or SMBus configuration
  • 3 selectable SMBus addresses
  • SMBus interface not required for device operation
  • Easy AC-coupling to other logic families, see application note AN-891.
  • Space saving 40-pin 5 × 5 mm VFQFPN

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
9DBL0641BKILF
Package Info
PCB Symbol, Footprint, and 3D Model
Active VFQFPN 40 I 100 Tray
Availability

Buy / Quote
9DBL0641BKILFT
Package Info
PCB Symbol, Footprint, and 3D Model
Active VFQFPN 40 I 100 Reel
Availability
Buy / Quote

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
9DBL02x2-04x2-06x1-08x1 Family Datasheet – Datasheet PDF 492 KB
User Guides & Manuals
Timing Products for NXP (Freescale) i.MX 简体中文 Guide PDF 321 KB
Application Notes & White Papers
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-839 RMS Phase Jitter – Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance – Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
Downloads
9DBL0641 IBIS Model – Model - IBIS ZIP 89 KB
9DBL06P1 IBIS Model – Model - IBIS ZIP 118 KB
Other
PCI Express Timing Solutions Overview – Overview PDF 275 KB
9DBL06xx Reference Schematic – Schematic PDF 118 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

Type Date
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 21, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Blog Post Dec 18, 2017
Why Fanout Buffers Make More Sense Blog Post Nov 28, 2017
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped News Dec 18, 2014