The 9DB403 is compatible with the Intel DB400v2 Differential Buffer Specification. This buffer provides 4 PCI Express® Gen2 clocks. The 9DB403 is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator.


  • 4 - 0.7 V current-mode differential output pairs
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 50-100 MHz operation in PLL mode
  • 50-400 MHz operation in Bypass mode
  • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread.
  • Supports undriven differential outputs in PD# and SRC_STOP# modes for power management.
  • Outputs cycle-cycle jitter < 50 ps
  • Outputs skew: 50 ps
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Phase jitter: PCIe Gen2 < 3.0/3.1 ps rms
  • 28-pin SSOP/TSSOP pacakge
  • Available in RoHS compliant packaging
  • Supports Commercial (0 to +70°C) and Industrial (-40 to +85°C) temperature ranges

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active SSOP 28 I Yes Tube
Active SSOP 28 I Yes Reel
Active SSOP 28 C Yes Tube
Active SSOP 28 C Yes Reel
Active TSSOP 28 I Yes Tube
Active TSSOP 28 I Yes Reel
Active TSSOP 28 C Yes Tube
Active TSSOP 28 C Yes Reel

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
9DB403D Datasheet Datasheet PDF 241 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Clock Distribution Overview 日本語 Overview PDF 217 KB
PCI Express Timing Solutions Overview Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB