8-output 1.8 V PCIe Gen1–4 Clock Generator with Zo=100 ohms
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Overview
Description
The 9FGV0841 is an 8-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo=100 Ω. The device has 8 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
For information regarding evaluation boards and material, please contact your local IDT sales representative.
Features
- PCIe Gen1–4 compliant
- Integrated terminations provide 100Ω differential Zo: reduced component count and board space
- 1.8V operation: reduced power consumption
- Outputs can optionally be supplied from any voltage between 1.05V and 1.8V: maximum power savings
- OE# pins: support DIF power management
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- DIF outputs blocked until PLL is locked: clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins: SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 6 × 6 mm 48-VFQFPN; minimal board space
- Selectable SMBus addresses: multiple devices can easily share an SMBus segment
- Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version (wettable flank package)
Applications
Documentation
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Application Note
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Guide
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Manual - Hardware
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Overview
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Overview
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Product Change Notice
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Schematic
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Product Options
Processing table
| VFQFPN | 48 | I | Yes | Tray | Get Samples, | |
| VFQFPN | 48 | I | Yes | Reel | ||
| VFQFPN | 48 | C | Yes | Tray | Get Samples, | |
| VFQFPN | 48 | C | Yes | Reel | ||
| VFQFPN | 48 | 2 | Yes | Tray | Get Samples, | |
| VFQFPN | 48 | 2 | Yes | Reel |
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play_circle_filledVideos & Training
PCIe Reference Clock Jitter Budgets
IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Video List
