Overview

The 5V41067A is a 2:4 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The 5V41067A selects between 1 of 2 differential HCSL inputs to fanout to 4 differential HCSL output pairs. The outputs can also be terminated to LVDS.

5V41067A - Block Diagram
5V41067A - Pinout
5V41067A - Block Diagram
5V41067A - Pinout
  • 4 – 0.7V current mode differential HCSL output pairs
  • Low additive jitter
  • suitable for use in PCIe Gen2 and Gen3 systems
  • 20-pin TSSOP package
  • small board footprint
  • Outputs can be terminated to LVDS
  • can drive a wider variety of devices
  • OE control pin
  • greater system power management
  • Industrial temperature range available
  • supports demanding embedded applications
  • Additive cycle-to-cycle jitter <5 ps
  • Additive phase jitter (PCIe Gen2/3) <0.2ps
  • Operating frequency up to 200MHz

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    5V41067APGG
    circleObsolete
    memory
    view_in_ar
    		TSSOP 20 C Yes Tube
    5V41067APGG8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 20 C Yes Reel
    5V41067APGGI
    circleObsolete
    memory
    view_in_ar
    		TSSOP 20 I Yes Tube
    5V41067APGGI8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 20 I Yes Reel
    Parametric Table tips

    Tips for Using This Parametric Table:

    • Hide Filters button in header: Collapse or expands filters
    • Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
    • Reset button in header: Reset all filters to the page default
    • Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
    • Export button in header: Export the filtered results of the table to an Excel document
    • Filter parts search bar in header: Type to filter table results by part number
    • Hide column button in column headers: Select to hide columns in table
    • AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
    • Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
    • Document icon next to product name in row: View the featured document for this product
    • Chip icon next to the right of the document icon in row: View the block diagram for this product
    • Cart icon to the right of the chip icon: Indicates that samples are available for this product
    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview