The 9ZXL0853E is a Gen1–5 compliant, enhanced performance differential clock buffer. The device supports complex clocking architectures like SRIS and SRNS. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0853E has an SMBus Write Lock feature for increased device and system security. The device also features up to 9 selectable SMBus addresses.
Features
- PCIe Gen1–5 compliance
- SMBus Write Protect feature; increase system security
- UPI/QPI support
- Supports PCIe SRIS and SNRS clocking
- LP-HCSL outputs with 85Ω Zout; eliminate 4 resistors per output pair
- 8 OE# pins; hardware control of each output
- 9 selectable SMBus addresses; multiple devices can share same SMBus segment
- Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz and 133.33MHz ZDB mode
- 6 × 6 mm 48-VFQFPN package; small board footprint