Clocks & Timing

Overview

The 9FGV1006 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1006 provides 2 copies of a of a single integer, fractional or spread-spectrum output frequency and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

9FGV1002C_9FGV1006C - Block Diagram
9FGV1006C - Pinout
9FGV1002C_9FGV1006C - Block Diagram
9FGV1006C - Pinout
  • PCIe Gen1–6 compliant
  • PCIe Gen6 Common Clock jitter < 50fs RMS
  • 276fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
  • 2 programmable output pairs plus 1 LVCMOS REF output
  • 1 integer, fractional or spread-spectrum output frequency per configuration
  • 1MHz–325MHz output frequency (LVDS or LP-HCSL)
  • 1MHz–200MHz output frequency (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V, 2.5V or 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – see AN-891
  • 3 × 3 mm 16-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software
Xilinx Versal ACAP Power and Timing
Xilinx UltraScale+ RFSoC Gen 1/2 ZU2x/3x Power and Timing
PCIe Nonvolatile Memory Express (NVMe) SSD Drive Solution

Documentation

Title Type Date
9FGV1002C-9FGV1006C Datasheet
PDF443 KB
Datasheet
AN-805 Recommended Ferrite Beads
PDF91 KB
Application Note
PLL Loop Filter Design and Fine Tuning
PDF1.16 MB
Application Note
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
Application Note
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output
PDF256 KB
Application Note
Driving Differential, Single-Ended, and/or Frequency Generator Crystal Inputs
PDF134 KB
Application Note
9FGV100x: PhiClock OTP Procedure
PDF222 KB
Application Note
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter
PDF486 KB
Application Note
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5
PDF244 KB
Application Note
AN-975 Cascading PLLs
PDF255 KB
Application Note
AN-918 Programmable Clocks vs Crystal Oscillators
PDF307 KB
Application Note
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs
PDF480 KB
Application Note
AN-879 Low-Power HCSL vs Traditional HCSL
PDF235 KB
Application Note
AN-843 PCI Express Reference Clock Requirements
PDF1.90 MB
Application Note
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
Application Note
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
Application Note
AN-839 RMS Phase Jitter
PDF233 KB
Application Note
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
Application Note
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
Application Note
AN-815 Understanding Jitter Units
PDF565 KB
Application Note
AN-802 Crystal-Measuring Oscillator Negative Resistance
PDF136 KB
Application Note
9FGV1006C001 Datasheet Addendum
PDF144 KB
Datasheet
9FGV1006C002 Datasheet Addendum
PDF144 KB
Datasheet
9FGV1006C015 Datasheet Addendum
PDF144 KB
Datasheet
9FGV1006CQ505 Datasheet Addendum
PDF144 KB
Datasheet
9FGV1006CQ506 Datasheet Addendum
PDF144 KB
Datasheet
9FGV1006CQ515 Datasheet Addendum
PDF144 KB
Datasheet
9FGV1006 Register Descriptions and Programming Guide
PDF323 KB
Manual - Software
9FGV1006 Timing Commander User Guide
PDF1.49 MB
Manual - Software
9FGV100x Register Descriptions and Programming Guide
PDF401 KB
Manual - Software
I2C GUI Tool User Guide
PDF507 KB
Other
PCI Express Timing Solutions Overview
PDF2.40 MB
Overview
IDT Clock Generation Overview
PDF1.83 MB
Overview
PCN# : PCN200009 (R1) PhiClock Family Revision Update
PDF129 KB
Product Change Notice
PCN# : PCN200009 PhiClock Family Revision Update
PDF143 KB
Product Change Notice
PCN# : MM1809-01 Die revision change,9FGV1006AnnnLTGI (8), 9FGV1006Q5nnLTGI (8)
PDF761 KB
Product Change Notice
9FGV1006 Reference Schematic
PDF52 KB
Schematic
PCIe Reference Clock Jitter Measurements for Gen5 and Beyond
PDF1.35 MB
White Paper

Design & Development

Software Downloads

Title Type Date
9FGV100x Fractional Timing Commander Personality File v1.4.2
7Z6.19 MB
Software & Tools - Other
I2C GUI Tool Software
ZIP9.27 MB
Software & Tools - Software

Boards & Kits

9FGV1006 - Evaluation Board (perspective)

EVK9FGV1006

Evaluation
Order Now

Evaluation Kit for 9FGV1006 Programmable PhiClock™ Generator

This is the evaluation board for the 9FGV1006 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the...

Featured Documents:
9FGV1006 / 9FGV1008 PhiClock PCIe Evaluation Board User Guide

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models

Models

Title Type Date
9FGV1006 IBIS Model
ZIP87 KB
Model - IBIS

Product Options

This device is factory-configurable. Try the Custom Part Configuration Utility.
    Processing table
    Part Number
    Output Type
    Output Impedance
    Supply Voltage (V)
    Xtal Freq (MHz)
    Carrier Type
    Buy / Sample
    9FGV1006C001LTGI
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    memory
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    Samples Available
    		 LP-HCSL 100 3.3 25 Tray
    9FGV1006C001LTGI8
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    memory
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    		LP-HCSL 100 3.3 25 Reel
    9FGV1006C002LTGI
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    memory
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    Samples Available
    		 LP-HCSL 100 1.8 25 Tray
    9FGV1006C002LTGI8
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    memory
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    		LP-HCSL 100 1.8 25 Reel
    9FGV1006C015LTGI
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    memory
    view_in_ar
    Samples Available
    		 LP-HCSL 85 3.3 25 Tray
    9FGV1006C015LTGI8
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    memory
    view_in_ar
    		LP-HCSL 85 3.3 25 Reel
    9FGV1006CQ505LTGI
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    memory
    view_in_ar
    Samples Available
    		 LP-HCSL 100 3.3 50 Tray
    9FGV1006CQ505LTGI8
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    memory
    view_in_ar
    		LP-HCSL 100 3.3 50 Reel
    9FGV1006CQ506LTGI
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    memory
    view_in_ar
    Samples Available
    		 LP-HCSL 100 1.8 50 Tray
    9FGV1006CQ506LTGI8
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    memory
    view_in_ar
    		LP-HCSL 100 1.8 50 Reel
    9FGV1006CQ515LTGI
    play_circleActive
    memory
    view_in_ar
    Samples Available
    		 LP-HCSL 85 3.3 50 Tray
    9FGV1006CQ515LTGI8
    play_circleActive
    memory
    view_in_ar
    		LP-HCSL 85 3.3 50 Reel
    Parametric Table tips

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    • Cart icon to the right of the chip icon: Indicates that samples are available for this product
    PCIe Reference Clock Jitter Budgets

    IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

    Video List
    PCIe Reference Clock Jitter Budgets
    PCIe Data Rates vs Clock Jitter Specs
    What Does PCIe Gen5 Say About SRIS?
    IDT PhiClock™ PCIe Gen 4 Clock Generators, 9FGV100x Family
    PCI Express (PCIe) Clock Overview by IDT
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
    Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling
    PCI Express (PCIe) Clock Generators by IDT
    PCI Express (PCIe) Clock Applications Overview by IDT
    PCI Express Gen 1 to Gen 4/Gen 5 Data Rate Evolution
    PCI Express Gen 1 to Gen 4/Gen 5 Clock Specification Evolution
    PCI Express Common Clock Jitter Model and Transfer Functions
    Comparing PCI Express® Gen 3-6 Jitter Filters to a 12k-20M Jitter Filter

    News & Blog Posts

    Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System Blog Post Apr 14, 2022
    Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility Blog Post Jun 14, 2019
    Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 22, 2018
    IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News May 1, 2018
    IDT Announces World’s Lowest-power PCI Express Timing Family News Aug 16, 2012