メモリ&ロジック

概要

The 5DB0148HA0 is a dual 4-bit bidirectional data buffer with differential strobes is designed for 1.1V, VDD operation. The device has a dual 4-bit host bus interface that is connected to a memory controller and a dual 4-bit DRAM interface that is connected to two x4 DRAMs. It also has an input-only control bus interface that is connected to a DDR5 Register.

5DB0148 - Block Diagram
5DB0148 - Pin Configuration
5DB0148 - Pin Assignment
5DB0148 - Block Diagram
5DB0148 - Pin Configuration
5DB0148 - Pin Assignment
  • Pinout optimized for DDR5 LRDIMM PCB layout
  • DDR5 Server speeds up to 4800MT/s
  • Supports power-down modes to conserve server power
  • Supports 1-rank / 2-rank DIMM configurations
  • Supports SDP and 3DS DRAM types
  • Provides access to internal control words for configuring device
  • Features and adapting to different LRDIMM and system applications
  • Loopback and pass-through modes
  • Training support features for DQ and MDQ interfaces
  • ZQ calibration

ドキュメント

タイトル 分類 日付
5DB0148HB0 Short-Form Datasheet
PDF131 KB
データシート－簡略版

設計・開発

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製品選択

    Processing table
    型名
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    5DB0148HA0AVG
    fast_forwardPreview
    memory
    view_in_ar
    		FCCSP 55 C Yes Tray
    5DB0148HA0AVG8
    fast_forwardPreview
    memory
    view_in_ar
    		FCCSP 55 C Yes Reel
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