概要

Double the drive of the standard 97U877 device. Low skew, low jitter PLL clock driver. 1 to 5 differential clock distribution (SSTL_18)

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

ドキュメント

= ピックアップ
分類 タイトル 日時
データシート
97U2A845A Datasheet
PDF 313 KB
EOL通知
PDN# : CQ-17-05 Quarterly Market Declined PDN
PDF 536 KB
2 items

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    97U2A845AHLF
    circle廃止品
    memory
    view_in_ar
    		CABGA 28 C Yes Tray
    97U2A845AHLFT
    circle廃止品
    memory
    view_in_ar
    		CABGA 28 C Yes Reel
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