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9ZXL1232E

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12-Output DB1200ZL PCIe Zero-Delay/Fanout Clock Buffer with SMBus Write Protection

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Features

  • SMBus write lock feature; increases system security
  • PCIe Gen 1–5 compliance
  • LP-HCSL outputs; eliminate 24 resistors, save 41mm² of area
  • 12 OE# pins; hardware control of each output
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz PLL mode; UPI and legacy QPI support
  • 9mm x 9mm 64-QFN package; small board footprint
Find Other Products in Application-Specific Clocks
9ZXL06x2E-08xxE-12x2E - Block Diagram
9ZXL1232E - Pinout
9ZXL06x2E-08xxE-12x2E - Block Diagram
9ZXL1232E - Pinout

Description

The 9ZXL1232E is a second-generation, enhanced-performance DB1200ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL1232A while offering a much-improved phase jitter performance and an SMBus Write Lock feature for increased system security. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL1232E has an SMBus Write Lockout pin for increased device and system security.

Parameters

Attributes Value
Temp. Range (°C) -40 to 85°C

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 9.0 x 9.0 x 0.9 64 0.5

Applications

  • Servers/High-performance computing
  • nVME storage
  • Networking
  • Accelerators
  • Industrial control

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Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.

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