特長
- Direct connection to 100Ω transmission lines; saves 24 resistors compared to standard PCIe devices
- 55mW typical power consumption in PLL mode; minimal power consumption
- Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- Spread spectrum tolerant; allows reduction of EMI
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- Pin/Software selectable PLL bandwidth and PLL bypass; minimize phase jitter for each application
- Outputs are blocked until PLL is locked; clean system start-up
- Configuration can be accomplished with strapping pins
- SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 5mm x 5mm 40-pin VFQFPN; minimal board space
- 3 selectable SMBus addresses; multiple devices can easily share an SMBus segment
説明
The 9DBV0641 6-output 1.8V PCIe fanout clock buffer is a member of Renesas' very-low power PCIe family. It has integrated output terminations providing Zo = 100Ω for direct connection to 100Ω transmission lines. The device has six output enable pins for clock management and three selectable SMBus addresses.
パラメータ
| 属性 | 値 |
|---|---|
| Diff. Outputs | 6 |
| Diff. Output Signaling | LP-HCSL |
| Output Freq Range (MHz) | 1 - 200 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 53 |
| Supply Voltage (V) | 1.8 - 1.8 |
| Output Type | LP-HCSL |
| Diff. Termination Resistors | 16 |
| Package Area (mm²) | 25 |
| Battery Backup | No |
| Battery Seal | No |
| CPU Supervisory Function POR | No |
| Crystal Frequency Trimming | No |
| Frequency Out Pin | No |
| Inputs (#) | 1 |
| Input Freq (MHz) | 30 - 175 |
| Divider Value | 1 |
| Additive Phase Jitter Typ RMS (fs) | 250 |
| Function | Zero Delay Buffer |
| Input Type | HCSL |
| Output Banks (#) | 1 |
| Core Voltage (V) | 1.8 |
| Output Voltage (V) | 0.8 |
| Product Category | PCI Express Clocks |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |