特長
- PCIe Gen6 付加位相ジッター: 4fs RMS
- PCIe Gen7 付加位相ジッター: 2.8fs RMS
- DB2000Q加算位相ジッタ:12fs RMS
- 12kHz–20MHzの加算位相ジッタ:156.25MHzで36fs RMS
- パワーダウン耐性(PDT)入力
- FSS機能(Flexible startup sequencing)
- SMBus 対応自動時計パーキング (ACP)
- CLKINはHCSLまたはLVDS信号レベルに対応しています
- 12個のLP-HCSL出力、インピーダンス85Ω
説明
9QXL1200 は、前世代の PCIe との下位互換性を備えた超高性能 PCIe Gen7 ファンアウト バッファです。 システムの監視と復元力のための信号損失(LOS)出力を備えています。 このデバイスには、パワーダウン耐性(PDT)および柔軟なスタートアップシーケンス(FSS)機能も組み込まれており、システム設計を簡素化します。
パラメータ
| 属性 | 値 |
|---|---|
| Temp. Range (°C) | -40 to 105°C |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| LGA | 5.0 x 5.0 x 0.66 | 64 | 0.5 |
製品比較
| 9QXL1200 | 9QXL2001C | |
| Core Voltage (V) | 3.3 | 3.3 |
| Output Impedance | 85 | 85 |
| App Jitter Compliance | DB1206, DB2000Q, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, PCIe Gen7, QPI, UPI | 25G EDR, DB2000Q, IF-UPI, PCIe Gen1, PCIe Gen2, PCIe Gen3, PCIe Gen4, PCIe Gen5, PCIe Gen6, QPI, UPI |
| VOUT Slew-rate Control | Yes | No |
| Additive Jitter | 4fs | 4fs |
アプリケーション
- クラウドとハイパフォーマンスコンピューティング
- NVMeストレージ
- ネットワーク
- AIアクセラレータ
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シミュレーションモデル
The RC family consists of PCIe Gen7 clock buffer and multiplexer solutions, providing the industry's smallest and most compact footprint.
A detailed overview of IDT's full-featured PCI Express (PCIe) clock and timing solutions. The presentation addresses PCIe Gen 1, Gen 2, Gen 3, and Gen 4 architectures and how IDT's industry-leading solutions provide all the functions, features, and performance required by the application.
Presented by Ron Wade, System Architect at IDT. For more information visit the PCIe clocks page.
A brief overview of the PCI Express common clock (CC) jitter model, and the transfer functions as they relate to the timing PLLs. This model applies to PCI Express (PCIe) Gen 2, Gen 3, Gen 4 and Gen 5. The equations would be slightly different for other PCIe architectures, such as SRIS, SRnS, or data clocked.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information about Renesas's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
This video compares PCIe Gen3–7 common clock jitter filters with a typical 12kHz to 20MHz plot to highlight the differences in filtering approaches.
A brief overview of how data rates have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT. For more information about IDT's PCIe timing solutions, visit the PCI Express (PCIe) Clocks page.
A brief overview of how clock and timing specifications have changed from PCI Express (PCIe) Generation 1, Gen 2, Gen 3, Gen 4 and Gen 5.
Presented by Ron Wade, system architect at IDT (acquired by Renesas). For more information, visit Renesas's PCIe Timing Solutions page.