特長
- Two selectable single-ended input reference clocks
- Eight single-ended clock outputs
- Internal PLL does not require external loop filter components
- 5V tolerant inputs
- Maximum output frequency: 160MHz, (2XQ output)
- Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)
- LVCMOS interface levels for all inputs and outputs
- PLL disable feature for low-frequency testing
- PLL lock output
- Selectable synchronization of output to input edge
- Output drive capability: ±24mA
- Output skew: 300ps (maximum), Q0:Q4
- Output skew: 500ps (maximum), all outputs
- Full 3.3V supply voltage
- Available in lead-free (RoHS 6) packages
- -40°C to 85°C ambient operating temperature
説明
The 870919I is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. Several output configurations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be disabled by the PLL_EN control signal to allow for low frequency or DC testing. The LOCK output asserts to indicate when phase-lock has been achieved. The 870919I device is a member of the HiperClocks family of high performance clock solutions from IDT.
