パッケージ情報
| CADモデル: | View CAD Model |
| Pkg. Type: | VFQFPN |
| Pkg. Code: | NLG56 |
| Lead Count (#): | 56 |
| Pkg. Dimensions (mm): | 8.0 x 8.0 x 0.85 |
| Pitch (mm): | 0.5 |
環境及び輸出分類情報
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
製品スペック
| Lead Count (#) | 56 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 3000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range (°C) | -40 to 85°C |
| Adjustable Phase | No |
| Advanced Features | Programmable Clock |
| C-C Jitter Max P-P (ps) | 25 |
| Core Voltage (V) | 3.3 |
| Divider Value | 1, 2, 3, 4, 6, 8, 16 |
| Feedback Divider | 324 - 648, 162 - 324 |
| Feedback Divider Resolution (bits) | 10 |
| Frequency Plan | 2500 / Output_Divider |
| Input Freq (MHz) | 16 - 16 |
| Input Ref. Divider Resolution (bits) | 1 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 2 |
| JESD204B/C Compliant | No |
| Length (mm) | 8 |
| MOQ | 3000 |
| Output Banks (#) | 2 |
| Output Divider Resolution (bits) | 3 |
| Output Freq Range (MHz) | 81 - 2592 |
| Output Signaling | LVPECL, LVDS |
| Output Skew (ps) | 15 |
| Output Type | LVPECL, LVDS |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 2 |
| Package Area (mm²) | 64 |
| Phase Noise Supports GSM | No |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 8.0 x 8.0 x 0.85 |
| Pkg. Type | VFQFPN |
| Prog. Clock | Yes |
| Prog. Interface | I2C |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 3.3 - 3.3 |
| Synthesis Mode | Integer |
| Tape & Reel | Yes |
| Thickness (mm) | 0.85 |
| Width (mm) | 8 |
| 掲載 | No |
844S42I に関するリソース
説明
The 844S42I is a 3.3V compatible, PLL based clock synthesizer targeted for clock generation in high-performance instrumentation, networking and computing applications. Using either the serial (I2C) or parallel programming interface, the 844S42I enables the generation of clock frequencies in the range of 81MHz to 2592MHz. The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS compatible clock signal can be used as PLL reference signal. The devices uses an integer-N synthesizer architecture and is optimized for low-jitter generation. The VCO within the PLL operates over a range of 1296MHz to 2592MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL post-dividers NA and NB are configured through either the I2C or the parallel interfaces, each can provide one of seven division ratios (1, 2, 3, 4, 6, 8, 16). This divider extends the performance of the part while providing a typical 50% duty cycle. The high-frequency outputs QA and QB are differential and are capable of driving a pair of transmission lines. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK_DT output. This device provides a clock enable control input that, when active (LOW), allows the outputs to switch normally, and when inactive (HIGH), places the outputs in a high impedance state. The 844S42I is packaged in a 8mm x 8mm 56-lead VFQFN package.