The 82EBP33831 Evaluation board for IEEE 1588 and Synchronous Ethernet allows the user to connect up to eight differential ended, up to eight single ended, and up to two Composite (AMI) reference inputs via SMA connectors. The inputs can operate at any frequency from 1PPS to 650MHz. Synchronization functions are provided by the IDT 82P33831 Digital PLL (DPLL) device which integrates two low jitter embedded clock synthesizers for Gigabit Ethernet and SONET/SDH PHYs and one ultra-low jitter embedded clock synthesizers for 10G/40G Gigabit Ethernet.
As well as clock inputs and outputs the evaluation board supports control and monitoring of the IDT 82P33831 device from a Windows computer using Timing Commander™over a USB interface. The board can also be connected via external ribbon cable to control the IDT 82P33831 directly via I2C for 1588 applications, in which SW controls the DCO using frequency or phase offsets.
The IDT 82EBP33814 low jitter output clocks can be used to directly synchronize 1G/10G/40G Gigabit Ethernet and SONET/SDH devices by connecting the evaluation board’s SMA connectors to reference clock inputs on the system board.
82EBP33831 Evaluation Board - top view
82EBP33831 Evaluation Board - side view
Suitable for evaluation of 82P33831 SETS & SMU device for 10GbE SyncE & IEEE 1588
Demonstrate the requirements of ITU-T G.8262 for EEC and ITU-T G.813 for SEC, with low-jitter clocks <0.3ps RMS (10kHz~20MHz)
Demonstrate the IEEE 1588 capability including DCO control, phase skewing & combo mode for meeting the requirements of ITU-T G.8263 for PEC-S-F and ITU-T G.8273.2 for T-BC