The evaluation kit supports the electrical evaluation process of the 8V19N882NVGI JESD204B/C clock jitter attenuator for all major device parameters including phase noise, spurious attenuation, clock frequency, output skew, phase alignment, device timing and the signal waveform. The device is a central source of phase-aligned clock and SYSREF signals in JESD204B/C applications. Its two stage PLL architecture is optimized for jitter attenuation and low phase noise, high frequency clock generation. The first stage PLL use an external VCXO component located on the evaluation board, the second stage uses an internal VCO or optionally, an external VCO. The internal VCO has a center frequency of 3.93216 GHz allowing the generation of wireless infrastructure reference frequencies. The optional external VCO component, when populated and selected, can be anywhere in the range of 700 MHz to 6 GHz supporting arbitrary frequency plans. The evaluation board has a footprint for the optional external VCO used in the 2nd stage PLL.
The board has SMA connectors to relevant I/O of the device: